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Figure
1-20 shows examples of asynchronous (un-clocked or combinatorial gates)
and synchronous (clocked flip-flop) logic. The notation used in this
site is representative of that used in most component specifications.
Timing specifications, such as delay, setup, and hold times, specify the
limits under which the device is guaranteed to operate as intended. If
those specifications are violated, the device may very well operate
correctly most of the time. However, a change in temperature, voltage,
or variations from unit to unit may make the circuit unreliable. The
most undesirable result of timing violations is that the circuit makes
very infrequent errors, perhaps one error in hundreds of hours of
operation. If you have ever wondered why your PC crashes mysteriously
for no apparent reason, timing specification violations may well be the
cause!Timing relationships are particularly important for signals that are "time shared" on a single wire. A group of wires that carries different information at different times is also called a bus.
