HPK taruh disini
A logic gate that is not forcing its output to be either one or zero is said to be tri-stated. Tri-state logic does not refer to base three numbers, but rather to a third invalid logic state when the output of a logic device is neither sinking nor sourcing current. This so-called third state is really an undefined condition, because the device output is not forcing a logic level on its output. It is said to be in a floating, high impedance, passive, or Hi-Z state, since the output circuits are effectively disconnected. A tri-state driver connected to one signal wire of the bus is shown in figure above.
On the left is an inverting buffer with an enabled tri-state output. On the fight side is an example showing two of the same type of buffers, with the top device in the disabled or passive state, and the lower device is enabled or actively driving the data bus to a logic one level. The control signal determines whether the output is passive or active, and is called the output enable or OE signal. The device shown above is actively driving the bus whenever the OE control line is at a logic one level, and is passive when the OE line is at a logic zero level. Most of the time, output enable signals are active low, meaning that the output is enabled when the/OE signal is low, and passive when the/OE signal is high. This is shown on the logic symbol with an inversion bubble where the enable signal enters the logic device.
