HPK taruh disini
The interconnection between the CPU, memory, and I/O of the address and data buses is generally a one-to-one connection. The hard part is designing the appropriate circuitry to adapt the control signals present on each device to be compatible with that of the other devices. The most basic control signals are generated by the CPU to control the data transfers between the CPU and memory, and between the CPU and I/O devices.
The four most common types of CPU controlled data transfers are:
1) CPU reads data/instructions from memory (memory read)
2) CPU writes data to memory (memory write)
3) CPU reads data from an input device (I/0 read)
4) CPU writes data to an output device (I/O write)
The address decode and control logic shown in Figure 1 is the key part of the design, which requires attention to timing analysis to guarantee signal logic and timing compatibility between the other blocks.
The simplified timing diagram for such a system is shown in Figure 2. Figure 2 is a genetic diagram and represents a typical example of a bus cycle for a typical CPU.
We see that there are two cycles:
The four most common types of CPU controlled data transfers are:
1) CPU reads data/instructions from memory (memory read)
2) CPU writes data to memory (memory write)
3) CPU reads data from an input device (I/0 read)
4) CPU writes data to an output device (I/O write)
The address decode and control logic shown in Figure 1 is the key part of the design, which requires attention to timing analysis to guarantee signal logic and timing compatibility between the other blocks.
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| Figure 1: Microcomputer busses. |
The simplified timing diagram for such a system is shown in Figure 2. Figure 2 is a genetic diagram and represents a typical example of a bus cycle for a typical CPU.
- Memory Read. The processor places an address on the address bus, and activates the memory read signal by pulling it low, which causes the selected memory location to be placed on the data bus.
- Memory Write. The processor places an address on the address bus, data to be written on the data bus, and activates the memory read signal by pulling it low, which causes the selected memory location to be loaded with the data the CPU placed on the data bus.
