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Timing notation is illustrated in Figure 1. The timing notation used in manufacturers' data sheets may vary from this, but is usually very similar. It is also important to notice that while the diagrams are reasonably standard, there is a wide variation in the selection of symbols for each timing parameter.
The purpose of timing analysis is to determine the sequence of events in each of the bus cycles so that we can delimit, among other things, the time available for each of the components to respond to changes. This time is compared to the requirements as specified in the manufacturers' data sheets to determine if they are compatible, and by what margin.
The most important timing specifications for interfacing components to a bus-oriented design are:
Propagation Delays
The propagation delay is the time it takes for a change at the input of a device to cause a change at the output. All devices--even wires--exhibit some propagation delay. Some devices do not have symmetrical delays for positive and negative transitions. In the Figure 3, the propagation times for a high to low transition are shorter than for a low to high transition. This asymmetrical delay is common for TTL and open collector and open drain outputs because they are better at sinking current than sourcing it. Thus, the load capacitance is charged more slowly when the current is being supplied from the weaker "high side" or pull-up device. Propagation delays are usually measured from the 50% amplitude points, as shown in Figure 3.
Setup and Hold Time
In Figure 4, a standard D type flip-flop (e.g., a 74xx74 device) is shown along with a sample timing diagram that illustrates the operation and key timing parameters of a flip-flop. This type of flip-flop samples the D input whenever the clock (CK) line goes high, and after a delay, the output remains in the same state until the next rising edge on the clock line. The triangle on the clock input indicates that it is a rising edge sensitive input, meaning that it will only have an effect when there is a rising edge on the clock pin. A falling edge sensitive input would have a bubble outside the block where the clock enters the flip-flop. In order to be able to guarantee that the flip-flop will operate correctly, the D input must be stable during the setup and hold time.
The purpose of timing analysis is to determine the sequence of events in each of the bus cycles so that we can delimit, among other things, the time available for each of the components to respond to changes. This time is compared to the requirements as specified in the manufacturers' data sheets to determine if they are compatible, and by what margin.
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| Figure 1: Timing diagram notation |
The most important timing specifications for interfacing components to a bus-oriented design are:
- Rise/fall time
- Propagation delay time
- Setup time
- Hold time
- Tri-state enable and disable delays
- Pulse width
- Clock frequency
There are two general classes of logic: combinatorial and sequential. Combinatorial logic has no memory and its output is some logical function of its current inputs, after some delay. Examples of combinatorial logic include gates, buffers, inverters, multiplexers, and decoders. Sequential logic has memory, which means that its outputs are a function of both current and past inputs. Examples of sequential logic are flip-flops, registers, microprocessors, and counters.
There are two types of sequential logic. Synchronous logic is synchronized to change only when there is a clock transition. In contrast, asynchronous logic does not use a clock signal. Almost all of the logic used in a microcomputer design will either be un-clocked asynchronous logic (gates, decoders) or clocked synchronous logic (counter, latch or microprocessor). Some types of devices are available in either form. Each of the timing specifications in the following discussion is described using simple logic devices as they are typically used in embedded computer designs.
Rise and Fall Times
The rise time of a signal is usually defined as the time required for a logic signal voltage to change from 20% to 80% of its final value. The fall time is from 80% to 20%, as shown in the figure below. These times are also commonly defined by some manufacturers as the transitions between the 10% and 90% levels. Figure 2 illustrates rise and fall times.
There are two types of sequential logic. Synchronous logic is synchronized to change only when there is a clock transition. In contrast, asynchronous logic does not use a clock signal. Almost all of the logic used in a microcomputer design will either be un-clocked asynchronous logic (gates, decoders) or clocked synchronous logic (counter, latch or microprocessor). Some types of devices are available in either form. Each of the timing specifications in the following discussion is described using simple logic devices as they are typically used in embedded computer designs.
Rise and Fall Times
The rise time of a signal is usually defined as the time required for a logic signal voltage to change from 20% to 80% of its final value. The fall time is from 80% to 20%, as shown in the figure below. These times are also commonly defined by some manufacturers as the transitions between the 10% and 90% levels. Figure 2 illustrates rise and fall times.
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| Figure 2: Rise and fall time of a signal |
Propagation Delays
The propagation delay is the time it takes for a change at the input of a device to cause a change at the output. All devices--even wires--exhibit some propagation delay. Some devices do not have symmetrical delays for positive and negative transitions. In the Figure 3, the propagation times for a high to low transition are shorter than for a low to high transition. This asymmetrical delay is common for TTL and open collector and open drain outputs because they are better at sinking current than sourcing it. Thus, the load capacitance is charged more slowly when the current is being supplied from the weaker "high side" or pull-up device. Propagation delays are usually measured from the 50% amplitude points, as shown in Figure 3.
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| Figure 3: Propagation delay |
Setup and Hold Time
In Figure 4, a standard D type flip-flop (e.g., a 74xx74 device) is shown along with a sample timing diagram that illustrates the operation and key timing parameters of a flip-flop. This type of flip-flop samples the D input whenever the clock (CK) line goes high, and after a delay, the output remains in the same state until the next rising edge on the clock line. The triangle on the clock input indicates that it is a rising edge sensitive input, meaning that it will only have an effect when there is a rising edge on the clock pin. A falling edge sensitive input would have a bubble outside the block where the clock enters the flip-flop. In order to be able to guarantee that the flip-flop will operate correctly, the D input must be stable during the setup and hold time.
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| Figure 4: Setup and hold time |
